// `include "counter.v"
// `include "fre_div.v"
// `include "edge_detect.v"

module stop_watch (
    input wire       clk       , //10MHz的时钟
    input wire       rst_n     , //异步复位，低电平有效
    input wire       clear     , //清零按钮，上升沿有效
    input wire       start_stop, //开始/暂停按钮，上升沿有效
    output wire [3:0] hr_h      , //时高位输出，取值0~9
    output wire [3:0] hr_l      , //时低位输出，取值0~9
    output wire [3:0] min_h     , //分高位输出，取值0~9
    output wire [3:0] min_l     , //分低位输出，取值0~9
    output wire [3:0] sec_h     , //秒高位输出，取值0~9
    output wire [3:0] sec_l       //秒低位输出，取值0~9
);

// 边沿检测，生成state_start状态信号
wire state_start;
edge_detect u_edge_detect(
    .clk         (clk         ),
    .rst_n       (rst_n       ),
    .clear       (clear       ),
    .start_stop  (start_stop  ),
    .state_start (state_start )
);



// 加一个分频器
wire clk_div;
fre_div 
#(
    .NUM_DIV (10)      // 仿真时10个时钟更新一次计数器值
)
u_fre_div(
    .clk     (clk     ),
    .rst_n   (rst_n   ),
    .clk_div (clk_div )
);

// sec_l
wire sec_l_cout;
counter 
#(
    .DW (4  ),
    .N  (10 )
)
u_sec_l(
    .clk         (clk         ),
    .rst_n       (rst_n       ),
    .clear       (clear       ),
    .state_start (state_start ),
    .cin         (clk_div     ),
    .val         (sec_l       ),
    .cout        (sec_l_cout  )
);
// sec_h
wire sec_h_cout;
counter 
#(
    .DW (4  ),
    .N  (6  )
)
u_sec_h(
    .clk         (clk         ),
    .rst_n       (rst_n       ),
    .clear       (clear       ),
    .state_start (state_start ),
    .cin         (sec_l_cout  ),
    .val         (sec_h       ),
    .cout        (sec_h_cout  )
);


// min_l
wire min_l_cout;
counter 
#(
    .DW (4  ),
    .N  (10 )
)
u_min_l(
    .clk         (clk         ),
    .rst_n       (rst_n       ),
    .clear       (clear       ),
    .state_start (state_start ),
    .cin         (sec_h_cout  ),
    .val         (min_l       ),
    .cout        (min_l_cout  )
);
// min_h
wire min_h_cout;
counter 
#(
    .DW (4  ),
    .N  (6  )
)
u_min_h(
    .clk         (clk         ),
    .rst_n       (rst_n       ),
    .clear       (clear       ),
    .state_start (state_start ),
    .cin         (min_l_cout  ),
    .val         (min_h       ),
    .cout        (min_h_cout  )
);


// hr_l
wire hr_l_cout;
counter 
#(
    .DW (4  ),
    .N  (10 )
)
u_hr_l(
    .clk         (clk         ),
    .rst_n       (rst_n       ),
    .clear       (clear       ),
    .state_start (state_start ),
    .cin         (min_h_cout  ),
    .val         (hr_l       ),
    .cout        (hr_l_cout  )
);
// hr_h
wire hr_h_cout;
counter 
#(
    .DW (4  ),
    .N  (10 )
)
u_hr_h(
    .clk         (clk         ),
    .rst_n       (rst_n       ),
    .clear       (clear       ),
    .state_start (state_start ),
    .cin         (hr_l_cout  ),
    .val         (hr_h       ),
    .cout        (hr_h_cout  )
);


endmodule